1. Field of the Invention
The present invention relates to a semiconductor device and to a method for manufacturing the same and, more particularly, to a pillar type stacked storage node of a semiconductor capacity and a method for fabricating the same.
2. Description of the Related Art
As DRAM devices are scaled down to a line width of about a quarter micrometer, two-dimensional areas occupied by capacitors become smaller. On the other hand, since the capacitance of a capacitor must be maintained at a constant level, methods have been developed to maintain a desired capacitance from decreased two-dimensional areas.
One approach is to form a capacitor that has a three-dimensional structure by increasing the height of the capacitor so as to increase available cell surface areas. The increase in the height of the capacitor, however, causes a large step between the cell array region and the peripheral region, thus making it difficult to form metal interconnections.
An alternative approach is to increase the dielectric constant of the dielectric film of the capacitor. Recently, high dielectric materials such as strontium titanate (SrTiO.sub.3), barium-strontium titanate ((Ba--Sr)TiO.sub.3), or the like having dielectric constant of more than 10,000, have been adopted for use as dielectric films. However, when polysilicon is used as a capacitor storage node, a layer of low dielectric characteristic is formed at the interface between the polysilicon layer and the high dielectric film, which thereby increases leakage current of the dielectric film.
Transition metals such as platinum (Pt) or the like are preferably used as a capacitor storage node when a high dielectric material, such as strontium titanate or barium-strontium titanate, is used as a dielectric film. However, there are also some problems when such transition metals are used in a high integrated circuit device. For example, in application, to about the range of 0.1 to 0.2 micrometers of spaced apart storage nodes, etched transition metal may be left deposited on sidewalls of the patterned storage nodes during a dry-etch process. As a result, an electrical bridge, i.e., a short, can arise between adjacent storage nodes.
A reference article, entitled "A Stacked Capacitor With An MOCVD (Ba--Sr)TiO.sub.3 Film And A RuO.sub.2 /Ru Storage Node On A TiN-capped Plug For 4Gbit DRAMs And Beyond," by H. Yamaguchi et al, IEDM 1996-675 relates to stacked storage nodes. FIG. 1 is a cross-sectional view showing a stacked storage node according to the above-identified reference. The stacked storage node is fabricated by forming a contact hole 15 in an insulating layer 14 on a semiconductor substrate 10 by EB (electron beam) lithography and RIE (reactive ion etching). A phosphorous doped polysilicon layer 16, about 2000.ANG. thick, is deposited in the contact hole 15 and on the insulating layer 14. The polysilicon layer 16 is then etched back to create a recess about 1000.ANG. from the top surface of the insulating layer 14 in the contact hole 15. Titanium is then deposited and annealed by RTA in N.sub.2 ambient to form a TiSix layer to reduce contact resistance. A 4000.ANG. thick barrier metal layer 17, such as a titanium nitride layer, is then deposited and planarized to form a storage contact plug 18 by chemical mechanical polishing. As for the storage node, a thick transition metal layer 19, about 4500.ANG., (double layer of 500.ANG. ruthenium and 4000.ANG. ruthenium dioxide) is deposited by DC sputtering with a Ru metal target. Then the transition metal layer 19 is etched to form the storage node 20 with 0.15 micrometer spacings between nodes. A high dielectric film 21 is then deposited on the insulating layer 14 and the storage node 20.
However, there are some problems with the above mentioned method. For example, it is very difficult to etch the transition metal layer with about 0.15 micrometer spacings between the nodes. As mentioned above, etched transition metal can be redeposited on sidewalls of the storage nodes during dry etch. As a result, a storage node may have a sloped sidewall profile, thus forming an electrical bridge between adjacent storage nodes.